System-on-Chip Test Architectures: Nanometer Design for Testability

Wang, Laung-Terng Stroud, Charles E. Touba, Nur

Ouvrage indisponible

Éditeur
Morgan Kaufmann Publishers In
Pages
896
Parution
janvier 2008
Format
Cartonné
Langue
Anglais
Dimensions
235 × 191 × 41 cm
EAN
9780123739735
  • Résumé

A guide to VLSI Testing and Design-for-Testability techniques that allows students, researchers, DFT practitioners, and VLSI designers to master System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs. It also includes practical problems at the end of each chapter for students.
Bio de l'auteur
Sommaire / contenu
Nous vous suggérons aussi
Retour en haut de page